A VHDL-based Design Methodology: the Design Experience of an High Performance ASIC Chip

In this paper we present a VHDL-based design methodology which we adopted in the design of an ASIC chip for real time image analysis in a quality control industrial environment. The design methodology is based on the following considerations: i) we explored the design space by applying some high level transformations on the VHDL speci cations; ii) we de ned some VHDL structural modeling (and design) guidelines to take into account, already in the rst design steps, some physical issues which, otherwise could cause incorrect behavior. The presented methodology proved to be e cient in avoiding design iterations and giving reliable high performance circuits.